Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due

to mispredicted branches with the always$-$taken predictor? Assume that branch outcomes

are determined in the MEM stage, that there are no data hazards, and that no delay slots are

used.

$(2)(4\%)$ Repeat $(1)$ for the $$always$-$not$-$taken$$ predictor.

$(3)(4\%)$ Repeat $(1)$ for the $2-$bit predictor$$ predictor.

$(4)(4\%)$ With the $2-$bit predictor, what speedup would be achieved if we could convert half of

the branch instructions in a way that replaces a branch instruction with an ALU

instruction? Assume that correctly and incorrectly predicted instructions have the same

chance of being replaced.

$(5)(4\%)$ With the $2-$bit predictor, what speedup would be achieved if we could convert half of

the branch instructions in a way that replaced each branch instruction with two ALU

instructions? Assume that correctly and incorrectly predicted instructions have the same

chance of being replaced.