#STUDENT_ID:1921089042

Task1. You are asked to design a small computing system with a customized N bits ISA that can execute the following high level codes: for (i=0, i< your student ID number , i++) Sum = Sum + (A[i] + 5) Note that N = Absolute of (value of your serial number -32). If the calculated value of N falls below 10 then add 10 more. For example, if your serial number is 30 then N = abs(30-32) =2, hence you need to design a (2+10) = 12 bits MIPS CPU. You need to use proper instruction type, and only three registers t0, t1, s1 to translate the given high level codes.

Q1(i) Assuming registers t0, t1 and s1 holding the value of ID number, i and Sum respectively, translate the above high level codes into MIPS code. Must indicate all the variable assignments and assumptions taken. (10 marks)

Q1(ii) Locate the data hazards into the MIPS codes from Q1(i) , if any. How can you solve those? Calculate the number of clock cycles required to perform the code correctly? Avoid stalls as much as possible. (10 marks)

Q1(iii) Draw a complete datapath for 5 stage pipelining (IF,ID,EX,MEM,WB) with pipeline registers that can perform the MIPS code from Q1(ii). Show the connectivity, the bus width of the connections and the width of the pipeline registers (in bits)s. (10 marks)

Q1(iv) Clearly indicate all ALU and Master control signals necessary to implement the datapath from Q1(iii). (10 marks) `

Q1(v) How much faster is your designed computing system with a perfect cache that never misses? Assume the following test values: (10 marks) instruction cache miss rate 10% data cache miss rate 20% miss penalty always 50 cycles CPI of 1 without memory stalls frequency of load/stores 40% of instructions