Suppose a system with byte-addressable memory uses a 32-bit virtual address and a 24-bit physical address. The pages are 4 KiB in length.

Consider a two-level paging approach in which the VPN is divided in half into a level-1 page number (high bits of VPN) and a level-2 page number (low bits of VPN). i. Draw a diagram showing the level-1 page number/level-2 page number/ offset division of bits in the virtual address. ii. For a process with a memory image of 512 KiB, how many level-1 page table entries are needed? iii. For a process with a memory image of 16 MiB, how many level-1 page table entries are needed?