Suppose that your chip has 100,000 gates and 4,800 flip-flops. A combinational ATPG produced 700 vectors to fully test the logic. A single scan-chain design will require about 106 clock cycles for testing. Find the scan test length if 12 scan chains is implemented. Given that the circuit has 12 Pls and 12 POs, and only one extra pin can be added for test, how much more gate overhead will be needed for the new design