Suppose we have a machine that takes in an infinite stream of bits, one bit at a time. On every input, the machine will output 0, unless the machine has seen the patttern 00100 in the last five inputs where it will instead output 1. Below is an example of this behavior.

Input: 00100100010100100...

Output: 00001001000000001...

a. Design a FSM that exibits the behavior described above.

b. Design a circuit that exibits the behavior decribed above, use D-Flip-Flops for memory, and use a one hot encoding design for the state registers. You can also use decoders, encoders, and multiplexors.