Suppose we have the following information Resource Latency in ps PC negligible I Mem 200 PC Add 50 Branch Add 50 All MUXs 25 REGs 100 ALU 150 SIGNEXT 10 Shift Left 2 5 D Mem 300 ALU Control 50 (a) (5 points) What is the clock cycle time for a non-pipeline processor? (b) (1 point) What is the clock cycle time for a pipelined processor? (c) (1 point) If we can split one stage of the pipeline datapath into two with equal latency, what will be the new clock cycle time?