Suppose you are designing a cache for a machine with 40-bit addresses. The cache is 1MB in size. Cache blocks are 64 bytes.

a. How many blocks can be held in the cache

b. How many bits of the address are devoted to the offset?

c. If the cache is direct-mapped, how many bits are devoted to the tag and index?

d. If the cache is 4-way set associative, how many bits are devoted to the tag and index? How many sets are there?

e. If the cache is fully associative, how many bits are devoted to the tag and index?