Suppose you have an instruction pipeline with five stages: instruction fetch (IF), instruction decode (ID), execution (EX), memory access (MEM), and write back (WB). Each stage has a latency of 2 clock cycles, and the pipeline is fully pipelined with no data hazards. The pipeline is initially empty, and the processor has just started executing a program.

Which of the following statements accurately describes the number of instructions that will have completed execution after 100 clock cycles?

A) 10 instructions will have completed execution.

B) 25 instructions will have completed execution.

C) 50 instructions will have completed execution.

D) 100 instructions will have completed execution.

Note: You may assume that the processor executes a mix of instructions that have different latencies, but on average, each instruction takes 10 clock cycles to execute.

Hint: Consider how many instructions can be in each stage of the pipeline at any given time, and how long it takes for an instruction to progress through each stage.