Suppose you have designed a 256 KB cache with 2 words data per block.

(a) Calculate the miss rate for the following memory address accesses. Memory is byte ad-dressable.

12, 42, 7, 15, 40, 39

(b) Suppose you have changed the cache design to 4 words data per block. Calculate the miss rate in this case for the scenario in part (a).

(c) Explain the principle of locality that caused the change in miss rate in (b)