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thanks in advance 1. Introduction After some initial analysis, UnasSoft found that Round Robin (RR) has better performance compared to other process scheduling algorithms namely

thanks in advance

1. Introduction

After some initial analysis, UnasSoft found that Round Robin (RR) has better performance compared to other process scheduling algorithms namely First-come, firstserved (FCFS), Shortest job next (SJN), and Shortest remaining time (SRT). However, to have a holistic analysis on the best time quantum according to the client specification, a list of jobs used by the client is provided to UnasSoft for further analysis.

Your tasks are to:

(a) Implement or code the Round Robin algorithm with C / C++ programing language.

(b) Use the program to read the provided job list. The job list for your group is provided separately in an excel file based on your group number.

(c) Evaluate the job list with different time quantum: [5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60], by determining the the following performance metrics:

(i) Turnaround time of the jobs;

(ii) Waiting time of the jobs; and

(iii) Number of interrupts incurred.

(d) Recommend the best time quantum for your job list based on your evaluation in

(c). Use suitable charts to explain and justify your recommendation.

(e) Prepare a 10 minute presentation that reports on the performance evaluation

of all time quantum and your recommendation of the best time quantum.

Assumptions

(a) All the arrived jobs are at Ready State and ready to be processed by CPU.

(b) Only ONE (1) CPU available for processing the jobs.

(c) Each context switching incurs ONE CPU CYCLE.

(d) Memory is always sufficient to hold any jobs.

(e) Each job has mixture of CPU and I/O instructions, and the integer between the

brackets indicates CPU or I/O cycle required for each instruction (Please refer to

the job list assigned to your group).

Example:

CPU (20) The integer 20 represents the computational instruction requires 20CPU cycle to compute.

I/O (40) The integer 40 represents the I/O instruction requires 40 CPU cycle to complete.

Job (1) arrive at CPU cycle 1 Job (2) arrive at CPU cycle 80 Job (3) arrive at CPU cycle 129 Job (4) arrive at CPU cycle 173 Job (5) arrive at CPU cycle 246 Job (6) arrive at CPU cycle 268 Job (7) arrive at CPU cycle 292 Job (8) arrive at CPU cycle 337 Job (9) arrive at CPU cycle 345 Job (10) arrive at CPU cycle 351
I/O (98) I/O (91) I/O (95) CPU (85) I/O (88) I/O (94) CPU (92) I/O (98) I/O (84) CPU (98)
CPU (96) I/O (83) I/O (100) CPU (90) I/O (87) CPU (99) CPU (82) I/O (84) I/O (86) I/O (92)
I/O (85) I/O (85) CPU (99) I/O (99) I/O (98) CPU (84) CPU (85) CPU (82) I/O (97) CPU (95)
I/O (90) CPU (99) I/O (93) I/O (83) CPU (93) I/O (97) CPU (94) CPU (96) I/O (97) I/O (100)
CPU (88) CPU (90) I/O (88) CPU (86) CPU (92) CPU (93) CPU (95) I/O (100) I/O (94) CPU (89)
CPU (94) I/O (86) CPU (81) I/O (84) CPU (98) I/O (90) I/O (88) CPU (89) I/O (83) I/O (97)
I/O (90) CPU (97) CPU (99) CPU (96) I/O (83) I/O (82) CPU (98) I/O (81) CPU (85) I/O (92)
I/O (94) CPU (93) CPU (93) I/O (84) CPU (84) I/O (94) I/O (85) CPU (93) I/O (88) CPU (99)
CPU (98) CPU (86) I/O (90) CPU (98) CPU (85) I/O (88) I/O (84) CPU (88) CPU (89) I/O (96)
CPU (96) I/O (94) I/O (81) I/O (89) CPU (89) I/O (95) I/O (82) CPU (88) CPU (95) CPU (100)
I/O (83) I/O (95) I/O (82) CPU (89) CPU (92) I/O (81) CPU (93) CPU (87) CPU (96) I/O (100)
I/O (98) I/O (82) CPU (99) I/O (97) I/O (93) CPU (87) I/O (98) CPU (100) I/O (91) I/O (88)
I/O (84) CPU (81) CPU (92) CPU (94) CPU (85) I/O (97) CPU (98) CPU (85) CPU (94) I/O (88)
I/O (100) I/O (89) CPU (82) I/O (93) I/O (87) CPU (98) CPU (84) I/O (98) CPU (88) CPU (92)
I/O (98) I/O (83) I/O (97) CPU (83) CPU (89) CPU (85) CPU (84) CPU (84) CPU (90) CPU (88)
I/O (81) I/O (82) CPU (98) I/O (88) CPU (83) CPU (90) CPU (93) CPU (93) CPU (95) CPU (90)
I/O (94) CPU (89) I/O (95) CPU (91) CPU (84) CPU (94) CPU (97) I/O (94) CPU (93) I/O (81)
I/O (91) I/O (89) I/O (99) I/O (89) I/O (83) CPU (81) I/O (94) CPU (84) I/O (100) I/O (93)
CPU (86) CPU (100) I/O (96) CPU (100) CPU (98) I/O (98) I/O (83) CPU (93) CPU (89) CPU (93)
CPU (98) I/O (99) I/O (90) I/O (83) I/O (98) I/O (92) I/O (96) I/O (84) I/O (88) CPU (91)
I/O (96) I/O (88) CPU (96) I/O (100) CPU (82) I/O (89) CPU (97) CPU (94) I/O (88) I/O (89)
CPU (82) CPU (97) CPU (84) I/O (84) CPU (99) CPU (94) CPU (84) I/O (99) I/O (82) CPU (98)
CPU (81) I/O (90) I/O (81) I/O (83) CPU (99) CPU (91) I/O (89) I/O (92) I/O (97) CPU (95)
CPU (97) CPU (97) CPU (81) CPU (86) I/O (85) I/O (90) CPU (93) CPU (98) CPU (93) I/O (96)
CPU (82) I/O (90) I/O (87) I/O (86) I/O (95) CPU (86) CPU (81) CPU (86) I/O (87) CPU (92)
CPU (96) I/O (96) I/O (98) CPU (91) CPU (90) I/O (99) I/O (84) I/O (85) CPU (90) I/O (83)
I/O (81) I/O (87) CPU (92) CPU (97) CPU (97) I/O (95) I/O (96) CPU (95) CPU (100) CPU (87)
I/O (84) CPU (86) I/O (89) I/O (88) I/O (87) I/O (91) I/O (96) CPU (90) CPU (92) I/O (89)
I/O (83) CPU (97) I/O (98) I/O (93) CPU (92) CPU (100) I/O (84) CPU (86) I/O (97) CPU (98)
CPU (89) I/O (87) I/O (84) CPU (85) I/O (84) CPU (92) I/O (99) CPU (100) CPU (81) CPU (85)
I/O (83) CPU (84) I/O (100) I/O (94) CPU (89) I/O (81) CPU (85) I/O (93) I/O (85) I/O (94)
CPU (83) CPU (99) I/O (82) I/O (99) CPU (92) CPU (81) I/O (88) I/O (87) I/O (85) I/O (85)
I/O (98) I/O (90) CPU (81) I/O (84) CPU (91) I/O (88) CPU (82) I/O (87) I/O (96) CPU (89)
I/O (81) I/O (100) CPU (86) I/O (88) CPU (94) CPU (86) I/O (91) CPU (85) I/O (97) I/O (93)
CPU (95) I/O (84) I/O (89) I/O (86) CPU (86) CPU (85) CPU (91) I/O (96) I/O (92) I/O (90)
I/O (100) I/O (89) I/O (82) I/O (95) I/O (91) I/O (94) CPU (81) I/O (85) CPU (95) I/O (91)

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