that is the whole question

2. Assume a five-stage single-pipeline micro architecture with Fetch, Decode/Register Read, Execute, Memory Access and Register Writeback and Result forwarding support between the pipeline stages. The operand value should be available to the instruction before the Execute stage. Using a multicycle pipeline diagram, demonstrate the progress of each instruction on every clock cycle until the last instruction of the first iteration of the following loop. Calculate the total number of cycles Loop: LH R2, 6(R1) SUB R6, R6, R2 SH R6, 6(R1) BEZ R6, Loop