The 5 stages of the processor have the following latencies: Assume Non-pipelined processor on a and b: - what is the cycle time? - What is the latency of an instruction? - What is the throughput? For the previous data mentioned in Question 1. If you could split one of the pipeline stages into 2 equal halves, which one would you choose? What is the new cycle time? What is the new latency? What is the new throughput