The answer to question a and b is figure 3.10 and 3.11

Please answer question c

Question 6: (a) Using a 4-bit version of the division algorithm, let's try dividing 00000111: by 0010. Please use 8-bit ALU, 4-bit quotient register, 8- bit divisor register, and 8-bit remainder register. Please write down a table with explanation, including the following columns, Iteration (starting with iteration 0), Quotient, Divisor, and Remainder, to show the contents stored in these registers while calculating the division results. (b) Please draw the optimized division machine schematics and explain how you make the optimization using 4-bit/8-bit ALU and Registers. Please describe the full control test logic for operating the optimized division machine you designed. (c) Explain how to convert the optimized division machine for multiplication (You don't need to draw another schematics, but you need to explain where to load the input binaries). Given 4-bit numbers, multiply 0010, with 0011 Please write down a table with explanation, including the following column, Iteration (starting with iteration 0) and Product, to show the contents stored in the 8 bit Product register while calculating the multiplication results. for Computers Chapter 3 Arithmetic Quotient DivisorR 0010 0000 0000 0010 0000 0010 00000000 0133 0001 0000 0000 01 0001 0000 0001 0000 0000 011 Step Iteration Initial values 1: Rem Rem-Dh 3: Shift Div 1: Rem- Rem-Div 0000 10000000 3 Shit Div right 1: Rem-Rem-Div 0000 10000000 011 3: Shift Div right 1: Rem Rem-Div 0000 0100 o 0000 01000000 0001 0001 0001 0 0010 | 0000 0000 0010 0000 00100000 000 0000 0001 0000 0001 3: Shift Div right 1: Rem Rem-Div 0011 FIGURE 3.10 Division example using the algorithm in Figure 3.9. The bit examined to determis the next step is circled in color 32 bits 32-bit ALU Remainder Control test Shift left 64 bits FIGURE 3.11 An Improved version of the division hardware. 4 bits Compari progra Quotient register ar all 32 bits wide, with only the Remainder register lftion also by fou the ALU and Divisor registers are halved and the remainder is shifted left. This Quotient register with the right half of the Remainder register. (As in Figure should really be 65 bits to make sure the carry out of the adder is not lost.) The Divisor registet, A Signed Division So far, we have ignorad rememb