1. The ARM Cortex uses various forms of branch predictions as fetched in F1, F3 and F4. In F1, a branch target buffer access retrieves a prediction of location and whether to branch or not so that the next cycle can fetch from the predicted location. On a miss, a hybrid branch predictor is consulted in F3, and if that buffer misses, an indirect branch predictor is accessed in F4. Assume the hit rates of these three buffers is 90%, 98% and 99.2%. In addition, if the instruction is a return, the predicted return location is retrieved off a return stack in F4 which we will assume has a 100% hit rate. Branches are determined in the EX2 stage so that a miss-prediction is only detected at that point. On a miss-prediction, the pipeline is flushed and refilled. If none of the accesses to buffers result in a hit, assume not taken is used until the EX2 stage where, if the branch is taken the pipeline is flushed and refilled. Assume we are running a benchmark with 20% branches where 16% are conditional branches, 3% are unconditional branches and 1% are returns. Assume a prediction rate of 85% for all conditional branches (this is the overall prediction accuracy of the three buffers), 98% for returns and 100% for unconditional branches. Assume the return buffer never misses. Assuming no other source of stalls, that two instructions issue every cycle, and an ideal CPI of .5, what is the actual CPI because of branches?