The block diagram of FIGURE 1 shows a 3-stage asynchronous counter that is used to count a series of randomly occurring input pulses. The Q outputs of the counter are used to drive a logic circuit that gives the output in TABLE 1. Design the logic circuit to realise the desired ABCD outputs. Input pulse 0 1 2 3 4 5 6 7 8 9 t 01 02 03 D 0 0 0 0 Counter 1 1 0 1 0 0 C 0 0 0 1 1 0 1 1 0 0 etc B 0 0 1 1 0 1 1 1 0 0 Logic A B C -D A 0 1 1 0 1 1 1 0 0 1