The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by Ais to Ao. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? Ans As4 CS Az 12 Ai 1. DA00 to DFFF 2. CA00 to CAFF 3. C800 to C8FF 4. C800 to CFFF