The circuit below consists of gates in which each INV/NOT has a delay of 3 ns. The OR and AND gates have 5 ns delays. Given an initial condition of A=0, B=1, C=0, and D=0, complete a timing diagram where C becomes 1 at 4 ns. Assume transport delay, and that the initial W, X, Y, and Z values are based on initial A, B, C, and D conditions. NO " 0- Ap D B X W