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The circuit shown below is intended to negate a 6-bit 2's complement number. For example, if the input aazajazaja, = 110100, then the output bsb.bb2bubo

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The circuit shown below is intended to negate a 6-bit 2's complement number. For example, if the input aazajazaja, = 110100, then the output bsb.bb2bubo = 001100. Note that the initial carry-in bit co is set to 1 in this design 24 az a a ao Bit C6 Bit Slice Bit Slice Bit Slice Bit Slice Bit Slice Co=1 Cg Slice C3 CA C1 bg b b b b. b. 1. Each bit slice is identical. Complete the truth table for a single bit slice and write the minimal SOP expressions. C ai Ci+1 b bi 0 0 0 1 1 0 1 1 Minimal SOP: Ci+1= Minimal SOP: b= 2. Assume that the band C+1 Outputs of each bit slice are implemented using 2-level AND-OR networks based on their minimal SOP expressions. In this question, count AND and OR gates, but do not count NOT gates. 4 How many gates are required in the entire circuit (all bit slices)? 4 How many gates are there along one of the longest paths from ag to bs? ^ 5 TO + : U The circuit shown below is intended to negate a 6-bit 2's complement number. For example, if the input aazajazaja, = 110100, then the output bsb.bb2bubo = 001100. Note that the initial carry-in bit co is set to 1 in this design 24 az a a ao Bit C6 Bit Slice Bit Slice Bit Slice Bit Slice Bit Slice Co=1 Cg Slice C3 CA C1 bg b b b b. b. 1. Each bit slice is identical. Complete the truth table for a single bit slice and write the minimal SOP expressions. C ai Ci+1 b bi 0 0 0 1 1 0 1 1 Minimal SOP: Ci+1= Minimal SOP: b= 2. Assume that the band C+1 Outputs of each bit slice are implemented using 2-level AND-OR networks based on their minimal SOP expressions. In this question, count AND and OR gates, but do not count NOT gates. 4 How many gates are required in the entire circuit (all bit slices)? 4 How many gates are there along one of the longest paths from ag to bs? ^ 5 TO + : U

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