The CSA-based multiplier circuit (scanned from Cavanagh and labelled A 4-bit carry-save array multiplier) appears to be suboptimal. In particular, two full adders in the first row have 0s as inputs whereas they could also have a0 AND b2 and a1 AND b2 as inputs, respectively. Doing more useful work earlier at no circuit cost should be an improvement. Try redrawing the circuit to maximize the number of full adders with three partial-product bit inputs (replacing a 0, a carry, or a sum from one or more of the full adder). Make sure it still works and that each FA has at most 3 inputs! Show your drawing. Does the timing change? Can you reduce the number of full adders?