The D latch we saw in the lecture was build using two AND gates, two NOR gates and an inverter, as shown in the figure below. Consider three other ways for obtaining a D latch. a. Use four NAND gates and an inverter. b. Use four NAND gates only (without an inverter). Hint: connect the output of the upper gate from (a) (i.e. the gate that goes to the $\mathrm{S}$ connection of the latch) to the input of the lower gate (i.e. the $\mathrm{R} $ connection, instead of the inverter output). c. Use NOR gates for all four gates. Inverters may be needed. cs.vs. 1249