The finite state machine (FSM) shown in the figure below is implemented with one toggle (T) flip-flop and one D flip-flop. It has a single input l and a single output Z. The combinational logic required is implemented by an 8:1 MUX, I NAND and 1 AND gates (a) Write the logic expressions for TA, DB and Z. (b) Obtain the state transition table including 1, QA, QB, Ta, DB, Qt, Qt and Z. [4 pts] (c) Draw the state transition diagram of the FSM including the IL/Z information. 3 pts] (d) Is this a Moore or a Mealy FSM? Justify 3 pts] (2 pts 013 M 0-4 U T Q 0-G D Q CLA CLK CLR te: Consult the flip-flop excitation table attached at the end as needed The finite state machine (FSM) shown in the figure below is implemented with one toggle (T) flip-flop and one D flip-flop. It has a single input l and a single output Z. The combinational logic required is implemented by an 8:1 MUX, I NAND and 1 AND gates (a) Write the logic expressions for TA, DB and Z. (b) Obtain the state transition table including 1, QA, QB, Ta, DB, Qt, Qt and Z. [4 pts] (c) Draw the state transition diagram of the FSM including the IL/Z information. 3 pts] (d) Is this a Moore or a Mealy FSM? Justify 3 pts] (2 pts 013 M 0-4 U T Q 0-G D Q CLA CLK CLR te: Consult the flip-flop excitation table attached at the end as needed