The first three most significant bits of IR (7-bit) are corresponding to the operation code (opcode). The instructions that your microprocessor needs to execute and the corresponding encodings are defined in Table 1. IR OPCODE Operation 000 aaaa 000 Load data (aaaa) to Accumulator (A) 001 aaaa 001 Add data (aaaa and Accumulator (A) 010 aaaa 010 Subtract data (aaaa) from Accumulator (A) 011 xxxx 011 Increment Accumulator (A) 100 xxxx 100 Decrement Accumulator (A) 101 aaaa 101 data (aaaa) AND Accumulator (A) 110 aaaa 110 data (aaaa) OR Accumulator (A) 111 aaaa 111 data (aaaa) XOR Accumulator (A) Control Circuit: FSM s_fetch s_decode s load s_dec s_add s_and 15 16 f7 0 f8 0 19 f103 f11 delete f12 insert scrol % 1 & GA backspoce Arithmetic Logic Unit (ALU): Selection Input 0 0 0 0 0 0 0 0 1 1 1 1 Operation A+B A-B A-1 A+1 A and B A or B not A A xor B 1 1 0 0 1 15 0 1 0 1 1 1 In the project report, include the VHDL codes for the given circuit and test bench. Force the inputs of IR (which are otherwise fetched from the program memory) so as to mimic the normal operation and test all the stages of operation Op mohamnet 66 The first three most significant bits of IR (7-bit) are corresponding to the operation code (opcode). The instructions that your microprocessor needs to execute and the corresponding encodings are defined in Table 1. IR OPCODE Operation 000 aaaa 000 Load data (aaaa) to Accumulator (A) 001 aaaa 001 Add data (aaaa and Accumulator (A) 010 aaaa 010 Subtract data (aaaa) from Accumulator (A) 011 xxxx 011 Increment Accumulator (A) 100 xxxx 100 Decrement Accumulator (A) 101 aaaa 101 data (aaaa) AND Accumulator (A) 110 aaaa 110 data (aaaa) OR Accumulator (A) 111 aaaa 111 data (aaaa) XOR Accumulator (A) Control Circuit: FSM s_fetch s_decode s load s_dec s_add s_and 15 16 f7 0 f8 0 19 f103 f11 delete f12 insert scrol % 1 & GA backspoce Arithmetic Logic Unit (ALU): Selection Input 0 0 0 0 0 0 0 0 1 1 1 1 Operation A+B A-B A-1 A+1 A and B A or B not A A xor B 1 1 0 0 1 15 0 1 0 1 1 1 In the project report, include the VHDL codes for the given circuit and test bench. Force the inputs of IR (which are otherwise fetched from the program memory) so as to mimic the normal operation and test all the stages of operation Op mohamnet 66