The following are part of a RISC architecture specifications: Section: 1. Eight 16-bit general purpose registers (8 registers and each register is 16 bits wide). 2. Special purpose register for the program counter (PC) 3. The instruction and the word size are 16-bit wide 4. Byte addressable memory 5. Little endian byte ordering 6. The ISA does not have SUBI instruction 7. Three Instruction types, with the following formats from the most significant to the R-Type: 4-bit opcode, 2-bit address mode, Rd, Rs, Rt, and the rest of bits are unuse 1-Type: 4-bit opcode, 2-bit address mode, Rd, Rs, and the rest of bits are for the ir J-Type: 4-bit opcode, 2-bit address mode, and the rest of bits are for the ir address). 8. The assembly syntax of some instructions of this architecture ADD/SUB/MUL Rd, Rs, Rt ADDI Rd, Rs, imm LW Rd, imm(Rs) SW Rd, imm(Rs) BLT/BEQ/BNE Rs, Rt, Label J Label

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what is the number and the size of the multiplexres needed