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The following canonical single-cycle datapath for a RISC-V architecture supports the base RISC-V architecture supports the base The follon rzisc-V I For the following questions,

The following canonical single-cycle datapath for a RISC-V architecture supports the base
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RISC-V architecture supports the base The follon rzisc-V I For the following questions, we want to expand our instruction set to support some new. instructions. For each of the proposed instructions below, choose ONE of the options below. A. Can be implemented without changing datapath wiring, only changes in control signals are needed. (i.e. change existing control signals to recognize the new instruction) B. Can be implemented, but needs changes in datapath wiring. only additional wiring. logical gates and muxes are needed. C. Can be implemented, but needs change in datapath wiring, and additional arithmetic units are needed (e.g. comparators, adders, shifters etc.). D. Cannot be implemented. Note that the options from A to D gradually add complexity, thus, selecting B implies that A is not sufficient. You should select the option that changes the datapath the least (e.g. do not select C if B is sufficient). You can assume that necessary changes in the control signals will be made if the datapath wiring is changed. 1) Allowing software to deal with 2's complement is very prone to error. Instead, we want to implement the negate instruction, neg rd,rs1, which puts - R[rs1] in R[rd]. 2) Sometimes, it is necessary to allow a program to self-destruct. Implement segtault

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