The following diagram represents the single-cycle datapath studied in class with support for a subset of the MIPS arithmetic-logic instructions, plus lw, sw, and beq. Control signals appear highlighted in blue. Branch RegWrite AluOp write PC in out address 25 21 MemWrite MemToReg 20.16 AluSrc instr read_index 1 read_data1 read_index2 read data2 write_index op1 zero result Adder4 -out in Instruction memory 15..11 op2 ALU write address read data Data memory write_data RegDst write_data Register file 15.0 in extend out Shift left out-op1 Adder result op2 MIPS instruction ; (jump) performs an unconditional jump to a destination address. The instruction is encoded using the J format, where field imm (bits 25..0) represents bits 27..2 of the target address (see MIPS reference card). Bits 1..0 of the target address are always 0, since the address of an instruction in memory is always a multiple of 4. Finally, bits 31..28 of the target address are taken directly from the 4 most significant bits of the current program counter (PC register). a) (7 pt.) Extend the datapath with support for instruction j. Your circuit should include a new control signal named jump. When set, the new datapath elements should provide the required functionality. When not set, the datapath should behave exactly as it did before your extension. You don't need to redraw the entire datapath. Draw the new datapath elements and connections, and draw only those components from the original datapath that are needed to understand the placement of your additions. For brevity, you can use labels to indicate the source or destination of wires connected to inputs and outputs of your new components. For example, if a wire comes from the instr output of the instruction memory, just label it InstMem.instr. If a wire's destination is the input of the PC register, just label it PC.in. use labels on your wires to indicate which omitted datapath elements they're connected to, e.g InstMem.instr[15:0] (imm) + SignExtend block b) (3 pt.) List the value that each control signal should take when instruction j is decoded. Specify a value equal to x (don't care) whenever the value of a specific control signal does not matter, that is, when a value set to 0 or to 1 would not make any difference in the execution of instruction j. Include an additional column for any new control signals. opcode func RegDst RegWrite Alusrc Aluop Branch MemWrite MemToReg Question 2 (10 pt.) MIPS instruction jal is used to invoke functions. It uses the same encoding as the j instruction, and it builds the target address identically. Its behavior is also very similar to j, but besides just jumping to a destination address, it also stores the return address in register $ra. The return address is the address that the invoked function should jump to once it finishes executing, and can be calculated as 4 plus the value of register PC at the time jal executes. a) (7 pt.) Extend the datapath to add support for instruction jal. Notice that all hardware used by ; will also be present for jal, so you don't need to write it again. Focus on the additional hardware needed to store the return address. Include a new control signal named jal. When set, the new hardware should activate and execute instruction jal. When not set, the datapath should behave as it did before with the j implemented in Question 1. b) (3 pt.) List the value for all signals of the control unit when instruction jal is decoded. Use x values (don't cares) when possible. Include an additional column for any new control signals
