The following Figure shows the process of going from a virtual address to a data item in cache. Answer the following questions based on this figure. $($a$)$ Is the TLB direct mapped, set associative, or full associative? Is the data cache, direct mapped, set associative, or fully associative? $($b$)$ What is the page size? What is the block size of the data cache? $($c$)$ What is the size of the data cache $($excluding the tags$)?$ What is the maximum size of physical memory supported in this memory system? $($d$)$ Is the cache virtually addressed or a physically addressed?