The following hypothetical machine is from Chapter 1 of our textbook:

In the following problem sets, we will use this expanded set of list of opcodes for our hypothetical machine:

0001 = Load AC from memory

0010 = Store AC to memory

0011 = Jump to address

0100 = Subtract memory from AC (result in AC)

0101 = Add to AC from memory (result in AC)

Perform program fetch/execute cycles for the following initial memory and program states. NOTE: one of the problems uses the Jump to address instruction to implement a loop. You do not need to simulate more than the 4 fetch/execute cycles for this problem, even though the program in principle would execute forever.

Fetch stage

Execute stage

	Memory	CPU registers
300	5940	300	PC
301	4941	3	AC
302	3301		IR
	. . .
940	0005
941	0001

Step 1

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 2

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 3

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 4

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 5

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 6

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step 7

	Memory	CPU registers
300			PC
301			AC
302			IR
	. . .
940
941

Step

34 Opcode Address (a) Instruction format 15 isT (b) Integer format Program counter (PC) = Address of instruction Instruction register (IR) = Instruction being executed Accumulator (AC) = Temporary storage (c) Internal CPU registers 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory (d) Partial list of opcodes Figure 1.3 Characteristics of a Hypothetical Machine 34 Opcode Address (a) Instruction format 15 isT (b) Integer format Program counter (PC) = Address of instruction Instruction register (IR) = Instruction being executed Accumulator (AC) = Temporary storage (c) Internal CPU registers 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory (d) Partial list of opcodes Figure 1.3 Characteristics of a Hypothetical Machine