The following questions concern the non-pipelined MIPS implementation, diagrammed above and MIPS instruction: AND $s, $t3, $t4

1. Convert the MIPS instruction to machine code and indicate the bits that are placed on the output lines of instruction memory. Trace the path of the instruction.

2. What is the CPI for every instruction in the above diagram?

Chapter 4 Material Add UI ALU Add Shift left 2 Branch MemRead Instruction 131-26 Control Instruction [25-21 Read Read address register 1 Read Instruction [20-16]Read data 1 register 2 ALU ALU 31-0] Instruction | Instruction [15-11] | U Read Address dataM M Write ata 2 register Write data Registers Write Data Instruction [15-0] 16 Sign 32 ALU extend Instruction [5-0 Figure 1: Non-pipelined MIPS Implementation Chapter 4 Material Add UI ALU Add Shift left 2 Branch MemRead Instruction 131-26 Control Instruction [25-21 Read Read address register 1 Read Instruction [20-16]Read data 1 register 2 ALU ALU 31-0] Instruction | Instruction [15-11] | U Read Address dataM M Write ata 2 register Write data Registers Write Data Instruction [15-0] 16 Sign 32 ALU extend Instruction [5-0 Figure 1: Non-pipelined MIPS Implementation