The following tables illustrate a list of RIS-V instruction formats and a list of RISC-V instructions and the corresponding opcode and funct3/func7 information. Core Instruction Formats xor or and sll srl sra slt sltu addi xori ori andi slli srli srai slti sltiu RV321 Base Integer Instructions Inst add sub lb 1h lw lbu 1hu sb sh SW beq bne blt bge bltu bgeu jal jalr lui auipc ecall ebreak Name: 31 Name ADD SUB XOR OR 27 26 25 24 funct7 rs2 imm[11:0] imm[11:5] imm [12 10:5] AND Shift Left Logical Shift Right Logical Shift Right Arith* Set Less Than Set Less Than (U) ADD Immediate XOR Immediate OR Immediate AND Immediate Shift Left Logical Imm Shift Right Logical Imm Shift Right Arith Imm Set Less Than Imm Store Byte Store Half Store Word Set Less Than Imm (U) Load Byte Load Half Load Word Load Byte (U) Load Half (U) Branch == Branch != Branch < Branch > Branch < (U) Branch > (U) rs2 rs2 imm[31:12] imm[20 10:1|11|19:12] Jump And Link Jump And Link Reg Load Upper Imm Add Upper Imm to PC Environment Call Environment Break I I 20 19. FMT Opcode R R R R R R R R R R I I I I I I I I I I I I S S S B B B B B B J I rs1 rs1 rs1 rs1 U U I I 15 14 12 11. funct3 rd funct3 rd funct3 imm[4:0] funct3 imm[4:1|11] rd rd funct3 0110011 0x0 0110011 0x0 0110011 0x4 0110011 0x6 0110011 0x7 0110011 0x1 0110011 0x5 0110011 0x5 0110011 0x2 0110011 0x3 0010011 0x0 0010011 0x4 0010011 0x6 0010011 0x7 0010011 0x1 0010011 0x5 0010011 0x5 0010011 0x2 0010011 0x3 0000011 exe 0000011 0x1 0000011 0x2 0000011 0x4 0000011 0x5 0100011 0x0 0100011 0x1 0100011 0x2 1100011 exe 1100011 0x1 1100011 0x4 1100011 0x5 1100011 0x6 1100011 0x7 1101111 1100111 0x0 0110111 0010111 1110011 0x0 1110011 0x0 funct7 0x00 0x20 0x00 0x00 0x00 0x00 0x00 0x20 0x00 0x00 7 imm=0x0 imm=0x1 Student ID: 6 0 Description (C) rd = rs1 + rs2 rd rs1 rs2 rd = rs1 rs2 rd rs1 < < rs2 rd = rs1 >> rs2 rd = rs1 >> rs2 rd rd rd rs1+ imm rd = rs1 imm rd rs1 | imm rd rs1 & imm rd imm[5:11]=0x00 imm[5:11]=0x00 imm[5:11]=0x20 rd rs1 >> imm[0:4] rs1 < < imm[0:4] rd = rs1 >> imm[0:4] (rs1 < imm)?1:0 rd rd rd rd rd rd M[rs1+imm][0:7] rd M[rs1+imm] [0:15] M[rs1+imm] [0:7] = rs2[0:7] M[rs1+imm] [0:15] = rs2[0:15] M[rs1+imm][0:31] = rs2[0:31] rs2) PC += imm if(rs1 != rs2) PC += imm if(rs1 rs2) PC += imm if(rs1 if(rs1 rs2) PC += imm if(rs1 rs2) PC += imm if(rs1 rs2) PC += imm PC+4; PC += imm PC+4; PC = rs1 + imm imm < < 12 PC+ (imm < <