The function L is defined as L(1) = 2,L(2) = 1,L(3) = 3,L(4) = 4 and for n 4

(a)Consider a pipelined processor. Describe what happens in the pipeline stages for the various types (data movement, data processing, control) of instructions.

We will use a five-stage pipeline:

IF (instruction fetch),

ID (instruction decode),

RR (register read),

EX (execute instruction),

WB (write back result into register).

Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not needed.

(b) Show the execution of your program on the above-pipelined processor for k = 6 by drawing a diagram. Assume that the fetched and decoded instructions are stored in an instruction window IW with unlimited capacity (and so you can store any number of instruction in the IW). Explain where and why delay slots appear

The rules for the execution of instructions are as follows:

1. All instructions go through the IF and ID stages.

2. For data-movement instructions the data transfer between the CPU and main memory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory bus.)

3. Immediate addressing for input arguments do not require RR or EX (e.g., LOAD r1, #X).

4. Arithmetic and logic instructions need RR, EX and WB.

5. Branching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB are required.

6. For the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be a register.

7. For the instruction STOR a, b the argument b must be an immediate address or register and a must be a memory location.

8. For each of the remaining instructions the arguments a, b and c must all be registers or immediate addresses.

9. You may assume for the sake of the assignment that the ISA supports floating-point arithmetic with no loss of precision

L(n+1) = L(n)+L(n 1)+L(n2)) L(n-3) L(n+1) = L(n)+L(n 1)+L(n2)) L(n-3)