Write a VHDL for the top-level design of the circuit in Figure (1). VHDL code of the components is listed in the appendix.

  
 

SW7 SW8 SW(6..0) SW9 KEY1 KEYO 1 I '0' UO do load run din reset_n clk U1 '0' do load run din reset_n clk q(0) q(0) lab08 U3 x(0) x(1) clk outp reset_n UO, U1, U2: shift_register U3: serial_adder_fsm UO, U1 : 7 bit wide, U2 8 bit wide Figure -1- '0' 0 U2 do load run din LEDR(7..0) reset_n clk q SW7 SW8 SW(6..0) SW9 KEY1 KEYO 1 I '0' UO do load run din reset_n clk U1 '0' do load run din reset_n clk q(0) q(0) lab08 U3 x(0) x(1) clk outp reset_n UO, U1, U2: shift_register U3: serial_adder_fsm UO, U1 : 7 bit wide, U2 8 bit wide Figure -1- '0' 0 U2 do load run din LEDR(7..0) reset_n clk q