The IE and IP registers of Intel $8051$ and the interrupt vector address table are given at the end. Configure the IE and IP registers to enable Timer $1$ and External Interrupt $1,$ but Timer $1$ with a higher interrupt priority than External Interrupt $1.$

A$.$ Draw the registers and show your values in hex, next to each register.

B$.$ How is Timer $1$ overflow detected and where will the execution jump when the

interrupt is serviced?

C$.$ While External Interrupt $1$ subroutine is running Timer $1$ overflows, causing a nested

interrupt. What will happen?