The objective of Lab $1$ is to write a Verilog module that displays the message $$Hello xxxx$$ or anything on the $7-$segment displays of your FPGA prototype board. To do this you will write a Verilog module that converts the ASCII. Problem $1)$ Complete the code above for all $26$ letters and $10$ numbers not just the ones you need for

your test.

Problem $2)$ Next you need to write the parent module in which the code above is an instance. This parent module that instantiates ASCII$27$Seg to display $$Hello OLH$($replace with your initials$)$ should look something like this in Verilog. Note, if you run a simulation of ASCIICodes you must force Kkey$0$ to $0$ or $1$ for it to choose a message. You can choose a ASII radix in ModelSim which will cause it to show $$Hello$$ and $$OLH$$ for the message, but you might as well use a radix of binary for the HexSeg variables. They are not ASCII codes and will not look in ModelSim like the letter or number.

Code is giving me errors please help me to correct them:

$//$ ASCII to $7$segment display coversation

module ASCII$27$Seg $($input $[7$:$0]$ AsciiCode, output reg $[6$:$0]$ HexSeg$)$;

always @$(*)$ begin

HexSeg $=7\text{'}$d$0//$ initialization of variable HexSeg

$display$("$AsciiCode $\%$b$",$ AsciiCode$)$;

case $($AsciiCode$)$

$//$Letter A

$8\text{'}$h$41$ : HexSeg$[3]=1$;

$//$Letter a

$8\text{'}$h$61$ : begin

HexSeg$[3]=1$;

end

$//$Letter B

$8\text{'}$h$42$ : begin

HexSeg$[0]=1$; HexSeg$[1]=1$;

end

$//$I finished the $1$st part

default : HexSeg $=8\text{'}$b$11111111$; $//$ Turn all the bits by default

module ASCIICodes $($input Kkey$0,$ output $[6$:$0]$ HexSeg$4,$ HexSeg$3,$ HexSeg$2,$ HexSeg$1,$ HexSeg$0)$;

reg $[7$:$0]$ Message $[4$:$0]$;

always @ $(*)$ begin

Message $[4]="$H$"$; $//$ Initialization of the message in each pass

Message $[3]="$E$"$;

Message $[2]="$L$"$;

Message $[1]="$L$"$;

Message $[0]="0"$;

case$($Kkey$0)$

$1\text{'}$b$1$ : begin

Message $[4]="$S$"$; $//$ Case for a parallel structure

Message $[3]="$T$"$;

Message $[2]="$E$"$;

Message $[1]="$V$"$;

Message $[0]="$E$"$;

end

default : begin

Message $[4]="$H$"$; $//$ Default to set message in every case

Message $[3]="$E$"$;

Message $[2]="$L$"$;

Message $[1]="$L$"$;

Message $[0]="0"$;

end

endcase

end

ASCII$27$Seg SevH$4($Message $[4],$ HexSeg$4)$;

ASCII$27$Seg SevH$3($Message $[3],$ HexSeg$3)$;

ASCII$27$Seg SevH$2($Message $[2],$ HexSeg$2)$;

ASCII$27$Seg SevH$1($Message $[1],$ HexSeg$1)$;

ASCII$27$Seg SevH$0($Message $[0],$ HexSeg$0)$;

endmodule