The objective of this assignment is to implement a parameterized carry save multiplier and Design of Digital Systems: Lab Assign

heavily test it using advanced techniques learned in VHDL$.$

Background

Multiplication, which is required by many hardware systems, is heavily studied since it is

a very expensive operation that requires a large area and long critical path to implement.

Carry$-$save multiplication is one technique that optimizes the standard ripple$-$carry multi$-$

plication by improving the critical path delay. Furthermore, in order to avoid any issues in

the design, the unit needs to be heavily tested using a large number of test vectors which

is usually generated using an external tool $($such as Matlab, Python, Magma, $...).$ VHDL

provides the textio library to allow reading from files which holds these test vectors

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I will need the design and the testbench file for vivado. Do not copy and paste from chat gpt$,$ please and thank you!

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The design should look like $--$ FULL$\_$ADDER COMPONENT

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity full$\_$adder is

port$($

$--$ add ports for full$\_$adder as described in the pdf

$)$;

end full$\_$adder;

architecture dataflow of full$\_$adder is

$--$ add signals here if needed

begin

$--$ write the architecture for full$\_$adder based on Figure $1$ schematic

end dataflow;

$--$ CARRY$\_$SAVE$\_$MULT COMPONENT

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity carry$\_$save$\_$mult is

$--$ add generic n

generic $()$;

port$($

$--$ add ports for carry$\_$save$\_$mult as described in the pdf

$)$;

end carry$\_$save$\_$mult;

architecture structural of carry$\_$save$\_$mult is

$--$ add full$\_$adder as component

$--$ variable array of n$-$bit std$\_$logic$\_$vector

type arr$2$d is array $($integer range $<>)$ of std$\_$logic$\_$vector$($n$-1$ downto

$0)$;

$--$ signal ab has dimensions $($n x n$)$

signal ab : arr$2$d$(0$ to n$-1)$;

$--$ full$\_$adder signals, all have dimension $(($n$-1)$ x n$)$

signal FA$\_$a : arr$2$d$(0$ to n$-2)$;

signal FA$\_$b : arr$2$d$(0$ to n$-2)$;

signal FA$\_$cin : arr$2$d$(0$ to n$-2)$;

signal FA$\_$sum : arr$2$d$(0$ to n$-2)$;

signal FA$\_$cout : arr$2$d$(0$ to n$-2)$;

begin

$--$ use nested for$-$generate to assign values to ab $2$D$-$array

gen$\_$ab$\_$rows: for i in $0$ to n$-1$ generate

gen$\_$ab$\_$cols: for j in $0$ to n$-1$ generate

$--$ write code here

end generate;

end generate;

$--$ Figure $3$ shows that we will use $(($n$-1)$ x n$)$ full adders

$--$ use nested for$-$generate to instantiate each full$\_$adder component.

$--$ ports are mapped to each bit of the $2$D$-$arrays FA$\_$a$,$ FA$\_$b$,$ FA$\_$cin,

FA$\_$sum, FA$\_$cout

$--$ after instantiating the full adders, we need to assign values

$--$ for the inputs of the FAs.

$--$ use the three patterns from the pdf to complete this part

$--$ and assign values to each row.

$--$ First row:

$--$ Intermediate rows:

$--$ Last row:

$--$ finally, do the last steps to compute the product.

$--$ Product:

end structural;

$--$ MULT WRAPPER

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity mult is

port$($

$--$ add ports for mult as described in the pdf

$)$;

end mult;

architecture structural of mult is

$--$ add carry$\_$save$\_$mult as a component

$--$ we don't need to the full$\_$adder as component here

$--$ signals

signal a$\_$reg : std$\_$logic$\_$vector$(7$ downto $0)$;

signal b$\_$reg : std$\_$logic$\_$vector$(7$ downto $0)$;

signal p$\_$s : std$\_$logic$\_$vector$(15$ downto $0)$;

begin

$--$ instantiate carry$\_$save$\_$mult $($create port map$)$

reg$\_$mult : process$($clk$)$

begin

if rising$\_$edge$($clk$)$ then

$--$ on the rising edge, make the signals equal

$--$ to the inputs and outputs carry$\_$save$\_$mult

end if;

end process;

end structural;

$--$ after completing the design, write the simulation testbench.

$--$ make sure to add "create clock $-$period $10-$name clk $[$get ports clk$]"$ to

your constraints file.

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The testbench should look like library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$textio.all;

library std;

use std$.$textio.all;

entity mult$\_$tb is

end mult$\_$tb;

architecture behavioral of mult$\_$tb is

$--$ ADD "mult$8$x$8.$dat" AS A SIMULATION SOURCE FIRST

$--$ file variable to read data from

file MULT$\_$FILE : text OPEN READ$\_$MODE is "mult$8$x$8.$dat";

$--$ create period constant

$--$ mult components

component mult is

$--$ add ports here

end component;

$--$ add signals

begin

$--$ instantiate mult component and complete the port map for it

$--$ generate the process for the clock similar to previous lab $0$ and

lab $2$

$--$ variables for reading for MULT$\_$FILE

tb: process

variable cur$\_$line : integer :$=1$;

variable v$\_$line : line;

variable v$\_$space : character;

variable v$\_$a : std$\_$logic$\_$vector$(7$ downto $0)$;

variable v$\_$b : std$\_$logic$\_$vector$(7$ downto $0)$;

variable v$\_$p$\_$exp : std$\_$logic$\_$vector$(15$ downto $0)$;

begin

$--$ useful functions

$--$ while not endfile$("$FILE$")$: keeps reading until reaching the end

of the file.

$--$ readline$("$FILE$",$"VARIABLE"$)$: reads $1$ line at a time from file

and stores it in variable.

$--$ hread$("$VARIABLE$",$ "VARIABLE"$)$: reads from the $1$st variable into

the $2$nd variable in HEX format.

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