The process of designing a synchronous counter that will count in a nonbinary sequence is primarily based on:

external logic circuits that decode the various states of the counter to apply the correct logic levels to the J-K inputs.

modifying asynchronous counters to change states on every second input clock pulse.

modifying BCD counters to change states on every second input clock pulse.

elimination of the counter stages and the addition of combinatorial logic circuits to produce the desired counts.