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The processor company has designed a new 1 0 stage pipeline ( shown below ) . The new pipeline is designed to perform better than

The processor company has designed a new 10
stage pipeline (shown below). The new pipeline is
designed to perform better than the standard 5-stage
pipeline. The useful results for the purpose of
forwarding are available at the last step in each stage
(F2, R1, X3, M3, W1). For example the ALU result
is not available until the end of the x2 stage.
F1 F2 R1 X1 X2 X3 M1 M2 M3 W1
11.1(5pt) Is it possible to eliminate data hazards
between R-type instructions in this pipeline by using
forwarding? Why or why not?
11.2(10pt) In the code fragments below, identify the
data hazards and describe the number of pipeline
stalls (or bubbles) required even with your full
bypassing.
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