The processor shows the instructions per cycle $($IPC$)$ of $0\mathrm{.}4$ for a program with out memory stalls. Suppose $40\%$ of instructions in the program are memory instructions $($i$.$e$.,$ loads$+$stores$),$ and the instruction cache has $100\%$ hit rate. What is the IPC when memory stalls are considered for the cache hit rates assumed in Problem $4\mathrm{.}1?$