The report should include the state diagrams, the Verilog codes and simulation waveforms for the design

1. a. Design an instruction decoder using the gate level constructs and test using Xilinx simulator. b. Design and simulate the Behavioral Model for the instruction decoder. The report should include the Verilog codes and simulation waveforms for the design Control[13:0] 00 0000 0000_0001 00 0001_0000_0000 00 0000 0000_0010 00 0000 0000_0100 00 0010 0000_0000 00 0000 0000 1000 00 0100 0000_0000 00 0000 0001_0000 00 1000 0000_0000 00 0000 0010_0000 01 0000 0000_0000 00 0000 0100_ 0000 00 0000_1000 0000 10 0000 0000_0000 Op-code 3:o] Address mode Immediate Memory Memory Immediate Memory Immediate Memory Immediate Memory Immediate Immediate Memory Memory Memory Mnemonic LDA 1000 0001 0010 1010 0011 1011 0100 1100 0101 1101 0110 0111 STA ADD SUB MUL SWAP PAUSE JC JV JZ Approach a. Generate the truth table for the given inputs and outputs b. Drawing the K-Maps for the obtained truth tables c. Gate level implementation for the expressions obtained d. A test bench e. Simulation f. Design the Behavioral model g. simulate using a test bench