The SystemVerilog design file and a screen capture of the output is required. I'm having the hardest time trying to get the output.

Your goal is to design and test a register file with 16 registers in SystemVerilog. A register file is the central storage of a microprocessor. Most operations involve using or modifying data stored in the register file. The register file that will be designed has 16 locations (e.g., RO, R1, etc.) CLK WE3 A1 RD1 A2 RD2 A3 Register WD3 File R15 Write a SystemVerilog hardware description of a register file. The register file should conform to the operation specified in the lecture, "Single-Cycle ARM Processor - Datapath," and shown in Figure 1. Below is arn example of how to create registers in SystemVerilog. You can test this code in EDAPlayground to see how it executes: // Register Design module register (input logic clk, input logic [3:0] d, output logic [3:0] q); always ff (posedge clk) endmodule // Register Testbench module tb_register); reg [3:0] d; reg clk; wire [3:0] q; register DUT (clk, d,q); initial begin $monitor("d %b q %b clk %b ", d,q, clk); Your goal is to design and test a register file with 16 registers in SystemVerilog. A register file is the central storage of a microprocessor. Most operations involve using or modifying data stored in the register file. The register file that will be designed has 16 locations (e.g., RO, R1, etc.) CLK WE3 A1 RD1 A2 RD2 A3 Register WD3 File R15 Write a SystemVerilog hardware description of a register file. The register file should conform to the operation specified in the lecture, "Single-Cycle ARM Processor - Datapath," and shown in Figure 1. Below is arn example of how to create registers in SystemVerilog. You can test this code in EDAPlayground to see how it executes: // Register Design module register (input logic clk, input logic [3:0] d, output logic [3:0] q); always ff (posedge clk) endmodule // Register Testbench module tb_register); reg [3:0] d; reg clk; wire [3:0] q; register DUT (clk, d,q); initial begin $monitor("d %b q %b clk %b ", d,q, clk)