The table shows the cycles per instruction and reflects the fact that our hardware includes a floating point co-processor:

You come up with two improvements to the design of the FP co-processor of the chip that our hardware uses. One of them reduces the number of cycles it takes to do the FP multiply or divide from 8 to 7; the other reduces the number of cycles for the FP add or subtract from 12 to 10.

A. Lets assume you only want to make one of your two possible enhancements. Purely on a performance basis, ignoring cost, which one would you recommend and why? (Justify your answer quantitatively.)

B. The potential improvement to the FP multiply/divide circuits would require 100,000 new transistors; the improvement to the FP add/subtract circuits would take 150,000. Now what is your final recommendation? Justify it quantitatively, of course. (And remember to consider that it may not be cost effective to do either alternative.)

Instruction ERAU Run Instruction Count Cycles Required Per Instruction 8 Floating point multiply or divide 7,000,000 Floating point add or subtract 12 2,000,000 All others (non floating point) 5 10,000,000 Instruction ERAU Run Instruction Count Cycles Required Per Instruction 8 Floating point multiply or divide 7,000,000 Floating point add or subtract 12 2,000,000 All others (non floating point) 5 10,000,000