the verilog code for Q$4$: Design a one$-$input, one$-$output serial $2$s complementor. The circuit accepts a string of bits from the input and generates the $2$s complement at the output. The circuit can be reset asynchronously to start and end the operation.

Test your circuit using the following input sequence. $1)010111110111100$

$2)$ Randomsequenceofyourchoice.