these codes in Verilog write it in VHDL

nshau-V-Notepad ia Edit Format Va Help module nsb_au_v (Func_Sel, Operand A, Operand_B, au_out, carryout) input [2:0] Func 5el; input 3:0] Operand_A, Operand_B; output [3:0] au.out, output carryout; wire [3:0] Y; ns Blaeic stage (func Salll, Func Sall,. aperand a, V) nsb 4bitadder stage (Fnc Sel[el, Operand A, Y, au out, carryout) n 1, Col1 8:38 PM O Type here to search nsh alu v-Notepad Fila Edit Format Viaw Help module nsb alu_v (Func_Sel, Operand _A, Operand , ALU_Result, ALU_Cout); input [3:0] Func_Sel, Operand A, Operand_B; output [3:0] ALU_Result; output ALU_Cout; wire [3:0] AU, LU; wire AUC, LU_C; nsb au stage0 (Func Sel[ 2:0], Operand A, Operand B, AU, AU C); stagel (Func Sel[2:1], OperandA, Operand B Lu, LU C); nsb 4mux?tol v stage? (FuncSel[3], A, AlU Result); nsb mux2tol stage3 (FncSel[3], AU C, LU C, ALU Cout) endmodule n 1, Col1 O Type here to search 8:39 PM 3/2019 nshau-V-Notepad ia Edit Format Va Help module nsb_au_v (Func_Sel, Operand A, Operand_B, au_out, carryout) input [2:0] Func 5el; input 3:0] Operand_A, Operand_B; output [3:0] au.out, output carryout; wire [3:0] Y; ns Blaeic stage (func Salll, Func Sall,. aperand a, V) nsb 4bitadder stage (Fnc Sel[el, Operand A, Y, au out, carryout) n 1, Col1 8:38 PM O Type here to search nsh alu v-Notepad Fila Edit Format Viaw Help module nsb alu_v (Func_Sel, Operand _A, Operand , ALU_Result, ALU_Cout); input [3:0] Func_Sel, Operand A, Operand_B; output [3:0] ALU_Result; output ALU_Cout; wire [3:0] AU, LU; wire AUC, LU_C; nsb au stage0 (Func Sel[ 2:0], Operand A, Operand B, AU, AU C); stagel (Func Sel[2:1], OperandA, Operand B Lu, LU C); nsb 4mux?tol v stage? (FuncSel[3], A, AlU Result); nsb mux2tol stage3 (FncSel[3], AU C, LU C, ALU Cout) endmodule n 1, Col1 O Type here to search 8:39 PM 3/2019