Think of the design of a sequential circuit$$ that emulates part of the instruction cycle with the following conditions:Inputs: indirect, program$-$check, C$1,$ clockOutputs: fetch, decode, indirect, execute, trap, S$1,$ S$2$States: fetch, decode, indirect, execute, trapState Transitions: All state transitions occur with the clock signal and each main state $($fetch$,$ decode, indirect, execute, trap$)$ cycles through two steps coincident with the clock $($so the machine transitions to the fetch state at$$S$1($written$$fetch$/$S$1)$ and then moves to the fetch state at$$S$2$where it transitions as given below: