This is a flashback to the "out there" question of the CS$2506,$ Spring'$22$ final exam. You are given a multicore processor with four $(4)$ processor cores. Each processor core has a private, one$-$level data cache with a capacity of $1$ Kilobyte $(1$ KB$)$ of data. The processor runs a program P which can be parallelized to exploit multiple cores and improve performance. When executed on a single core, program P achieves an ideal CPI of $1\mathrm{.}0.$ The ideal CPI is achieved when there are no stalls due to cache misses. When the program uses the cache, the program spends an additional $1\mathrm{.}0$ cycles per instruction to resolve compulsory and conflict misses in the processor core's cache. The program also incurs capacity misses. The additional cycles per instruction that the program spends due to capacity misses is $1\mathrm{.}0$ when the program runs on a single core. Answer the following questions: Assume that the portion of the CPI due to capacity misses in a program P