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This question concerns software interlocking to resolve read - after - write hazards in pipelined CPU execution. Consider an ARM 5 - stage pipeline with

This question concerns software interlocking to resolve read-after-
write hazards in pipelined CPU execution. Consider an ARM 5-stage
pipeline with no forwarding and hazard detection. How many NOPS
should be inserted in the following instruction sequence so all
hazard are eliminated and between where?
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