$`$timescale $1$ns $/1$ps

module TestBenchForCache;

$//$ Inputs

reg clk;

reg reset;

reg $[31$:$0]$ read$\_$data;

$//$ Outputs

wire $[31$:$0]$ pc;

wire $[31$:$0]$ alu$\_$result;

wire $[31$:$0]$ write$\_$data;

$//$ Instantiate the RISC$-$V Single Cycle Processor

RiscV$\_$SingleCycle uut $($

$.$clk$($clk$),$

$.$reset$($reset$),$

$.$pc$($pc$),$

$.$alu$\_$result$($alu$\_$result$),$

$.$write$\_$data$($write$\_$data$),$

$.$read$\_$data$($read$\_$data$)$

$)$;

$//$ Clock generation

initial begin

clk $=0$;

forever #$5$ clk $=$ ~clk;

end

$//$ Task to display register contents

task display$\_$registers;

integer i;

begin

$display$("$Registers:$")$;

for $($i $=0$; i $<32$; i $=$ i $+1)$ begin

$display$("$x$\%0$d: $\%$h$",$ i$,$ uut.registers$[$i$])$;

end

end

endtask

$//$ Task to display memory contents

task display$\_$memory;

integer i;

begin

$display$("$Memory:$")$;

for $($i $=0$; i $<1024$; i $=$ i $+1)$ begin

if $($uut$.$memory$[$i$]!==32\text{'}$h$00000000)//$ Display non$-$zero memory locations

$display$("$Address $\%0$d: $\%$h$",$ i$,$ uut.memory$[$i$])$;

end

end

endtask

$//$ Testbench procedure

initial begin

$//$ Initialize Inputs

reset $=1$;

read$\_$data $=32\text{'}$h$00000000$;

$//$ Load instructions into instruction memory

$//$ ADDI instructions to load values into registers

uut.instruction$\_$memory$[0]=32\text{'}$b$00000000000100000000000010010011$; $//$ ADDI x$1,$ x$0,1$

uut.instruction$\_$memory$[1]=32\text{'}$b$00000000001000000000000100010011$; $//$ ADDI x$2,$ x$0,2$

uut.instruction$\_$memory$[2]=32\text{'}$b$00000000001100000000000110010011$; $//$ ADDI x$3,$ x$0,3$

uut.instruction$\_$memory$[3]=32\text{'}$b$00000000010000000000001000010011$; $//$ ADDI x$4,$ x$0,4$

$//$ Memory read $($hit$)$

uut.instruction$\_$memory$[4]=32\text{'}$b$00000000000100010000001010000011$; $//$ LW x$5,1($x$2)--$ Should hit

$//$ Memory read $($miss$)$

uut.instruction$\_$memory$[5]=32\text{'}$b$00000000001000010000001100000011$; $//$ LW x$6,2($x$2)--$ Should miss

$//$ Memory write $($hit$)$

uut.instruction$\_$memory$[6]=32\text{'}$b$00000000000100010000001100100011$; $//$ SW x$1,2($x$2)--$ Should hit

$//$ Memory write $($miss$)$

uut.instruction$\_$memory$[7]=32\text{'}$b$00000000001100010000001100100011$; $//$ SW x$3,2($x$2)--$ Should miss

$//$ JAL instruction to end the test and loop indefinitely

uut.instruction$\_$memory$[8]=32\text{'}$b$00000000000000000000000001101111$; $//$ JAL x$0,0$

$//$ Initialize memory with values for hit and miss scenarios

$//$ Memory hits

uut.memory$[3]=32\text{'}$h$12345678$; $//$ Address $3$

uut.memory$[4]=32\text{'}$h$9$abcdef$0$; $//$ Address $4$

$//$ Memory misses will access uninitialized memory addresses

$//$ Release reset

#$10$ reset $=0$;

$//$ Run simulation for a sufficient time to observe behavior

#$200$ display$\_$registers;

#$200$ display$\_$memory;

$//$ Run simulation for a sufficient time to observe behavior

#$400$ display$\_$registers;

#$400$ display$\_$memory;

#$600$ $finish;

end

$//$ Monitor the outputs

initial begin

$monitor$("$Time: $\%$t$,$ PC: $\%$d$,$ ALU Result: $\%$d$,$ Write Data: $\%$d$",$

$time, pc$,$ alu$\_$result, write$\_$data$)$;

end

$//$ VCD file generation

initial begin

$dumpfile$("$TestBenchForCache$.$vcd$")$; $//$ Specify the name of the VCD file

$dumpvars$(0,$ TestBenchForCache$)$; $//$ Dump all variables in this module

end

endmodule WHY THIS CODE ALU$\_$RESULT XXXXX$?$ HOW I CAN EDIT?