timescale lns / lps /the CPU module from 4. 13.4 of the textbook from the online compani on material /The initial register and memory state are read from.dat files and the /resulting register and memory state are each printed into correspondi ng dat /files 6 8 module CPU (clock); parameter LW = 6'b100011, SW=6'b101011, BEQ=6'b000100, no-op 32'b0000000-0000000-0000000-0000000, ALUop -6'bo, BNE -6' b000101; integer fd,code,str,t; input clock; 13 14 regl31:0] PC, Regs [0:31], IMemory [0:1023], DMemory [0:1023], // separate memories IFIDIR, IDEXA, IDEXB, IDEXIR, EXMEMIR, EXMEMB, // pipeline registers EXMEMALUOut, MEMNBValue, MEMNBIR; // pipeline registers 17 18 wire [4:0] IDEXrs, IDEXrt, EXMEMrd, MEMNBrd, EXMEMrt, IFIDrs, IFIDrt; //hold register fields wire [5:0] EXMEMop, MEMNBop, IDEXop, IFIDop; //Hold opcodes wire [31:0] Ain, Bin; 20 21 //declare the bypass signal s wire takebranch, stall, bypassAfromMEM, bypassAfromALUinWB, bypassBfromMEM, bypassBfromALUinWB 24 25 26 | O 27 . O 28 | O 29 . O bypassAfromLWinWB, bypassBfromLWinWB; wire bypassIDEXAfromWB, bypassIDEXBf romWB: assign IDEXTs 1DEXIRI25:21]; assign IDEXTt = IDEXTR[20:16]; assign EXMEMrd = EXMEMIRI15:11); assign EXMEMrt = EXMEMIRI20:16]; assign MEMWBrd = MEMWBIR[15:11]; assign EXMEMop = EXMEMIR[31:26]; assign MEMWBop = MEMWBIR[31:26]; assign IDEXop 1DEXIRI31:26]; assign IF1Dop -IFIDIRI31:26]; assign IF1Drs = IFIDIR[25:21]; assign IF1Drt = IFIDIR[20:16]