TLB is 4-way Set Associative and cache is 2-way set associative. Given: 32-bit virtual memory, 4 KB page size, 32 GB of physical memory, index for the TLB is 11 bits. For the cache, the tag has 17 bits and the byte offset is 4 bits.

1. How many bits in the physical memory address?

2. How many indices in the TLB?

3. How many bits in the TLB tag?

4. How may bits in the TLB physical page number?

5. How many bytes are required to implement our 4-way set associative TLB? Include 1 valid bit, 1 dirty bit, and 2 protection bits.

6. What kind of logic gate would make a good comparator to compare the tag in the TLB with the virtual address bits to determine a TLB hit. Output is high if they match.

7. If the page table were to be implemented as an array with one entry for every virtual address, is there still an advantage to using a TLB? Why or why not? (Guessing yes or no gets no points.)

8. How many bits in the index into the cache from the physical address?

9. How many bytes per block?

10. How large is this cache?

11. How much memory would be required to implement this cache?

12. Briefly describe a scenario that would cause a cache block to be replaced. Be specific to this cache.

13. My C program executes the following function call: memcpy ( 0x121000, 0x9CFF0, 5 * 1024); How many different entries in the TLB are accessed? Briefly explain how you arrived at your answer.