Total Marks: $10$Objectives: Build a single$-$cycle MIPS processor. Modify the MIPS processor design to include more instructionsContents:$1.$ Introduction$2.$ MIPS Single$-$cycle processor$3.$ Testing the processor$4.$ Modifying the Single$-$Cycle processor$5.$ Testing the modified processor$6.$ Assignment$1.$ INTRODUCTIONIn this lab you will build a simplified MIPS single$-$cycle processor using Verilog. You will combine your ALU from Lab $8$ with the code for the rest of the processor. Then you will load a test program and confirm that the system works. Next, you will implement two new instructions, and then write a new test program that confirms the new instructions work as well. By the end of this lab, you should thoroughly understand the internal operation of the MIPS single$-$cycle processor.Please read and follow the instructions in this lab carefully. In the past, many students have lost points for silly errors like not printing all the signals requested.Before starting this lab, you should be very familiar with the single$-$cycle implementation of the MIPS processor described in your text. The single$-$cycle processor schematic from the text is repeated at the end of this lab assignment for your convenience. This version of the MIPS single$-$ cycle processor can execute the following instructions: add, sub, and, or$,$ slt$,$ lw$,$ sw$,$ beq, addi, and j$.$Our model of the single$-$cycle MIPS processor divides the machine into two major units: the control and the datapath. Each unit is constructed from various functional blocks. For example, as shown in the figure on the last page of this lab, the datapath contains the $32-$bit ALU that you designed in Lab $8,$ the register file, the sign extension logic, and five multiplexers to choose appropriate operands. $2.$ MIPS SINGLE$-$CYCLE PROCESSORThe Verilog single$-$cycle MIPS module is given to you below. Copy them to your own lab$9\_$xx folder.Study the files until you are familiar with their contents. Look in mips.v at the mips module, which instantiates two sub$-$modules, controller and datapath. Then take a look at the controller module and its submodules. It contains two sub$-$modules: maindec and aludec. The maindec module produces all control signals except those for the ALU. The aludec module produces the control signal, alucontrol$[2$:$0],$ for the ALU. Make sure you thoroughly understand the controller module. Correlate signal names in the Verilog code with the wires on the schematic.After you thoroughly understand the controller module, take a look at the datapath Verilog module. The datapath has quite a few submodules. Make sure you understand why each submodule is there and where each is located on the MIPS single$-$cycle processor schematic. Youll notice that the alu module is not defined. Copy your ALU from Lab $8$ into your lab$9\_$xx directory. Be sure the module name matches the instance module name $($alu$),$ and make sure the inputs and outputs are in the same order as in they are expected in the datapath module.The highest$-$level module, top, includes the instruction and data memories as well as the processors. Each of the memories is a $64-$word$\backslash$times $32-$bit array. The instruction memory needs to contain some initial values representing the program. The test program is given to you below. Study the program until you understand what it does. The machine language code for the program must stored in memfile.dat. Use QtSPIM to generate the corresponding machine language code.IMPORTANT: You must use the simulator in bare machine mode by clicking the Bare Machine button from Simulator$->$Settings$->$MIPS.A Bare Machine is one which does not have anything in it$.$ The Memory is blank $,$ there is no OS and hence no separate address spaces. The first thing that will run on the bare machine will be your program. In this program the instructions start from the lowest memory address of $0.$ Data starts from an address further down.If QtSpim is not set to Bare Machine mode it will calculate the branch address differently $($instead of PC$+4,$ it will add the displacement to PC$).$Since QtSpim is meant to simulate a MIPS program running along an OS$,$ the program is given address spaces in specific regions $($Instructions from $0$x$00400000$ and Data from $0$x$10010000).$ The Jump instruction will concatenate the current PC address. Since the PC is in a particular address space $(0$x$00400000)$ the jump addresses will also be different. Also QtSpim has start up user program code that loads your program. Hence even if QtSpim is set to Bare Machine mode there still might be an error in the Jump Addresses because of these cases. Hence you will have to double check and make sure that both the branch and jump addresses being placed in your machine instructions are correct according to a bare machine, in which your program is the only thing running in the machine with Instructions starting at the Memory Address of $0.$ Figure $1$: mips.v Single Cycle MIPS processor verlog codeFigure $2.$ MIPS assembly program: test$1.$asmQuestion $1$: If you single$-$step through the program you will get an exception error, Explain Why?$3.$ TESTING THE SINGLE$-$CYCLE MIPS PROCESSOR$3\mathrm{.}1$ SimulationIn this section, you will test the processor with your ALU.In a complex system, if you dont know what to expect the answer should be$,$ you are unlikely to get the right answer. Begin by predicting what should happen on each cycle when running the program. Complete the chart in Table $1$ at the end of the lab with your predictions. What address will the final sw instruction write to and what value will it write?Simulate your processor with Xilinx ISE. Refer to your earlier lab handouts if you need a refresher on how to use Xilinx ISE. Be sure to add all of the $.$v files, including the one containing your ALU. Add all of the signals from Table $1$ to your waves window. $($Note that many are not at the top level; youll have to drill down into the appropriate part of the hierarchy to find them.$)$Run the simulation. If all goes well, the testbench will print Simulation succeeded. Look at the waveforms and check that they match your predictions in Table $1.$ If they dont, the problem is likely in your ALU or because you didnt properly add all of the files. If you need to debug, youll likely want to view more internal signals. However, on the final waveform that you turn in$,$ show ONLY the following signals in this order: clk$,$ reset, pc$,$ instr, aluout, writedata, memwrite, and readdata. All the values need to be output in hexadecimal and must be readable to get full credit.After you have fixed any bugs, print out your final waveform. Figure $3$: testbench for Single Cycle MIPS