uestion \#1: Assume we have a processor that implements Tomasulo's algorithm with ROB with the following ecifications: - ROB has 8 entries - One common data bus (CDB) - Each functional unit has two reservation stations - Two un-pipelined floating point dividers. Each one has a latency of 12 clock cycles - One 8-stage pipelined floating point unit that can perform floating point addition, substation, and multiplication - One 2-stage pipelined load-store unit Trace the execution of the following code snippet on this processor. This includes: - The content of the reservation stations, the register file, and the ROB at each clock cycle - At each clock cycle, which pipeline stage of which instruction is executed. - What is the CPI of this code snippet on this processor? fld f6,32(x2) fld f2,44(x3) fmu1.d0,f2,f4 fsub. d f8,f2,f6 fdiv,d0,f0,f6 fadd. d f6,f8,f2